1. Technical Field
The present invention relates to a power on reset circuit employed in an integrated chip (IC) and the like, and particularly, to a power on reset circuit capable of even being in a circuit requiring a sleep mode or the IC requiring low power consumption.
2. Description of the Related Art
A power on reset (hereinafter, abbreviated as ‘POR’) circuit is a circuit necessary for an integrated chip (IC) including a digital circuit. A digital block needs a structure in which the digital block is not automatically turned on while power VDD is applied thereto but data stored in the digital block is reset by input of a predetermined pulse. To this end, after the power VDD is applied and a predetermined time is delayed, the input of the pulse is required. However, the POR always needs to consume current. Therefore, it is difficult to use the POR in a circuit requiring a sleep mode or a circuit needed to have small power consumption.
FIG. 1 is a view showing an example of a POR circuit according to the related art.
Referring to FIG. 1, the POR circuit according to related art is configured of a current mirror circuit 110, an inverter 120, and a delay capacitor 130.
When the VDD is applied as the power, current ratio is adjusted by the current mirror circuit 110 so as to mirror current IA to be smaller. In addition, the small IA current charges the delay capacitor and voltage of a “point A” obtains voltage delayed as compared to the VDD. This may obtain more delayed pulse than the VDD through the inverter 120. FIG. 2 is a view showing a simulation result for the POR circuit as described above.
However, in the case of the POR circuit according to related art as described above, since the current mirror circuit 110 always operates, it consumes significantly large power. In addition, since the current mirror circuit 110 always operates as described above, it is difficult to use in the case requiring the sleep mode or in the case of the IC requiring low power.